The present invention relates generally to communication networks, and, more particularly, to a base transceiver station that reduces congestion in a communication network.
A communication network typically includes base transceiver stations (BTSs) for connecting devices, such as user equipment (UE) of the communication network. A BTS and UE communicate using RF signals in accordance with communication standards such as Long-Term Evolution (LTE), LTE-Advanced (LTE-A), High Speed Packet Access (HSPA), and other third generation partnership project (3GPP) standards.
FIG. 1 is a schematic block diagram of a conventional BTS 100. The BTS 100 is in communication with multiple UE and other network devices (not shown). The BTS 100 includes a hardware accelerator 102, a processor 104, a level-2 (L2) cache memory 106, a random access memory (RAM) 108, a level-3 (L3) cache memory 110, and an antenna interface system (AIS) 112 that are connected by way of first and second system busses 114 and 116, as shown. The first and second system busses 114 and 116 may be Advanced Extensible Interconnect (AXI) system busses.
The AIS 112 receives uplink RF signals (i.e., uplink real-time (RT) data) from a UE (not shown) and stores the uplink RT data in the L2 cache memory 106 (i.e., in antenna buffers of the L2 cache memory 106). The processor 104 fetches the uplink RT data from the L2 cache memory 106 and processes the data to acquire uplink information. The processor 104 generates downlink RT data, based on intermediate downlink data received from upper layers (such as layer 3) and stores the downlink RT data in the L2 cache memory 106 (i.e., in the antenna buffers). The AIS 112 fetches the downlink RT data from the L2 cache memory 106 and transmits it to the UE.
If the L2 cache memory 106 is busy servicing a memory request from any component of the BTS 100, the L2 cache memory 106 may be inaccessible to the other components. For example, if the L2 cache memory 106 is busy servicing a memory request generated by the hardware accelerator 102, the L2 cache memory 106 may be inaccessible to the processor 104 and the AIS 112. Further, if there is a cache miss in the L2 cache memory 106, the L2 cache memory 106 fetches the required data from the L3 cache memory 110 (or the RAM 108) by way of the second system bus 116. Thus, if the L2 cache memory 106 is inaccessible to the AIS 112 when uplink RT data is received by the AIS 112, the AIS 112 cannot store the uplink RT data in the L2 cache memory 106, leading to an over-run of the uplink antenna buffers, and hence, loss of the uplink RT data. Similarly, if the L2 cache memory 106 is busy servicing a memory request, the L2 cache memory 106 may be inaccessible to the AIS 112 for a longer period of time, causing an under-run of the downlink antenna buffers and disrupting the synchronization between the BTS 100 and the UE. This technique is inefficient as it does not provide deterministic data flow for streaming time-critical uplink and downlink RT data, leading to congestion in the communication network.
Known techniques to overcome the aforementioned problem include using the L2 cache memory 106 only for uplink and down-link RT data, increasing the size of the L2 cache memory 106, or increasing the number of interfaces with the L2 cache memory 106. These techniques result in an increase in circuit area, and are not efficient.
It would be advantageous to have a BTS that reduces congestion in the communication network and reduces instances of communication failure.